SiFive unveils RISC-V chip design for high-performance AI workloads – TechnoNews

SiFive, a designer of chips based mostly on the RISC-V computing platform, introduced a collection of recent AI chips for high-performance AI workloads.

The SiFive Intelligence XM Sequence is designed for accelerating excessive efficiency AI workloads. That is the primary mental property from SiFive to incorporate a extremely scalable AI matrix engine, which accelerates time to marketplace for semiconductor firms constructing system on chip options for edge IoT, shopper gadgets, subsequent era electrical and/or autonomous automobiles, knowledge facilities, and past.

As a part of SiFive’s plan to help clients and the broader RISC-V ecosystem, SiFive additionally introduced its intention to open supply a reference implementation of its SiFive Kernel Library (SKL).

The announcement was made at a SiFive press occasion, Tuesday, in Santa Clara, the place executives mentioned the management function the RISC-V structure is taking part in on the core of AI options throughout a various vary of market leaders, and supplied an replace on SiFive’s technique, roadmap and enterprise momentum.

The open resolution

Patrick Little, CEO of SiFive, mentioned in an interview with VentureBeat that clients within the semiconductor, methods and shopper markets have come to understand the software program technique behind SiFive and RISC-V.

He famous that merchandise with greater than 10 billion SiFive cores have shipped to this point. And Little famous that SiFive has invested greater than $500 million in R&D and it’s promoting to the highest semiconductor leaders and hyperscalers. The corporate has greater than 400 design wins.

The RISC-V structure has a software program that’s an open normal interface, that means any sorts of cores that hook up with it. Meaning clients who use SiFive designs can select their very own accelerators for AI and different functions with out having to fret about breaking software program compatibility, Little mentioned.

Whereas massive leaders in AI like Nvidia can use their very own proprietary graphics processing unit (GPU) architectures, smaller firms use their very own breed of accelerators, he mentioned. However software program programmers don’t wish to study a brand new language each time a brand new accelerator comes alongside, Little mentioned. So the hyperscalars and chip firms wish to use RISC-V options like SiFive so that they don’t should hold rewriting their software program, he mentioned.

The RISC-V open normal software program interface permits for the swish evolution of the RISC-V normal over time and it de-risks the answer past a single proprietary vendor.

SiFive has been steadily transferring up a meals chain, beginning within the Nineties with embedded cores and including its first vector processor in 2021. And now it’s including AI options. Clients can use it as an information circulate processor because the entrance finish to their processor to go together with their altering backend AI accelerators.

“They don’t want to keep writing to the AI software. So we put a RISC-V vector processor in front of that. The AI processors keep changing fast. The models keep changing. Software writers want to write to something that will be around in 15 years,” he mentioned. “We are one of the few companies that can fill that gap. And today we announced own accelerator, or matrix multiplication engine, and we are doing the XM product line to completement what we did in vector processing. It’s a matrix multiplication engine.”

Clients who need an alternative choice to Nvidia can flip to a different supply, however they don’t need that rival to be one other proprietary resolution. Reasonably, they like RISC-V because it affords many rival firms behind it, Little mentioned.

“We believe our solution can scale to Nvidia level performance,” he mentioned.

“Many companies are seeing the benefits of an open processor standard while they race to keep up with the rapid pace of change with AI. AI plays to SiFive’s strengths with performance per watt and our unique ability to help customers customize their solutions,” mentioned Little. “We’re already supplying our RISC-V solutions to five of the Magnificent 7 companies, and as companies pivot to a ‘software first’ design strategy we are working on new AI solutions with a wide variety of companies from automotive to datacenter and the intelligent edge and IoT.”

SiFive’s new XM Sequence affords a particularly scalable and environment friendly AI compute engine. By integrating scalar, vector, and matrix engines, XM Sequence clients can benefit from very environment friendly reminiscence bandwidth. The XM Sequence additionally continues SiFive’s legacy of providing extraordinarily excessive efficiency per watt for compute-intensive functions.

“RISC-V was originally developed to efficiently support specialized computing engines including mixed-precision operations,” mentioned Krste Asanovic, SiFive chief architect, in a press release. “This, coupled with the inclusion of efficient vector instructions and the support of specialized AI extensions, are the reasons why many of the largest datacenter companies have already adopted RISC-V AI accelerators.”

As a part of his presentation, Asnovic launched extra particulars on the brand new XM Sequence which broadens its Intelligence Product household. The XM Sequence additionally continues SiFive’s legacy of providing extraordinarily excessive efficiency per watt for compute-intensive functions.

That includes 4 X-Cores per cluster, a cluster can ship 16 TOPS (INT8) or 8 TFLOPS (BF16) per GHz. The chip has 1TB/s of sustained reminiscence bandwidth per XM Sequence cluster, with the clusters having the ability to entry reminiscence by way of a excessive bandwidth port or by way of a CHI port for coherent reminiscence entry. SiFive envisions the creation of methods incorporating no host CPU or ones based mostly on RISC-V, x86 or Arm. The corporate is sampling its options now.

SiFive will likely be on the RISC-V Summit North America, going down Oct. 22-23, 2024 in Santa Clara, California. The corporate has 500 individuals.

“We’ve become the gold standard of RISC-V,” Little mentioned.